library verilog;
use verilog.vl_types.all;
entity DDS_model is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        key             : in     vl_logic;
        model_sel       : in     vl_logic_vector(1 downto 0);
        Fword           : in     vl_logic_vector(31 downto 0);
        Pword           : in     vl_logic_vector(11 downto 0);
        data            : out    vl_logic_vector(13 downto 0)
    );
end DDS_model;
